1. Technical Field
The present invention relates generally to processor power-state transitions and, more particularly, to programmable power-state transition controllers for facilitating power-state transitions.
2. Description of the Related Art
Technical advances have enabled faster and more powerful processors to be used in a variety of applications. Often the increases in speed and processing power come at the expense of increased power consumption and processor size. In some applications, the increased power consumption is a potential issue, such as applications that have limited power sources. To address the concerns related to the increased power consumption, some processor systems implement one or more power saving modes. The system enters the power saving modes to save power or to reduce the amount of heat generated. Examples of such power-saving modes are taught by U.S. Pat. No. 6,714,891 (Method and Apparatus for Thermal Management of a Power Supply to a High Performance Processor in a Computer System), U.S. Pat. No. 6,393,573 (Power Management for Automotive Multimedia System) and U.S. Pat. No. 6,446,213 (Software-Based Sleep Control of Operating System Directed Power Management System with Minimum Advanced Configuration Power Interface (ACPI)-Implementing Hardware) and are fully incorporated herein by reference.
Power-saving modes are sometimes implemented by transitioning the frequency of the processor clock or by varying an input voltage of the processor. The transitions are often facilitated using hardwired circuits. These hardwired circuits can be constructed so as to require minimal control from the processor and can be designed for minimal power consumption. However, the hardwired circuits are difficult to implement because they do not allow for simple modifications after they are created. Thus, they must be redesigned whenever the transition protocol changes due to a change in the application or the processor.
The power-state transitions can also be facilitated using software executed by the main processor. This solution can be problematic because the processor must devote some of its processing time to the transition, which can cause undesirable performance issues in applications where the processor is expected to provide real-time responses. Additionally, the extra processing required by the processor consumes even more power.
Another solution is to facilitate the power-state transitions using a programmable logic device. Programmable logic devices provide flexibility in their functionality; however, they often consume excess power because they are designed for multiple uses. For instance, programmable logic devices often have excess circuitry to facilitate modification of their internal configuration. Moreover, programmable logic devices typically have unused logic.
These and other limitations present challenges to the implementation of processor power management.